1. Field of the Invention
The present invention relates to a controller that controls a machine tool, and in particular, to a controller that executes a sequential program using a multi-core processor.
2. Description of the Related Art
FIG. 16 is a diagram depicting a conventional numerical controller that executes a sequential program using a multi-core processor.
The numerical controller 10 includes a numerical control section 11, a PMC section 12, a servo motor control section 13, and an amplifier interface section 14. The numerical control section 11 includes a processor core 20, a first-level cache memory (L1 cache) 21, a second-level cache memory (L2 cache) 22, a DRAM 24, and a peripheral LSI 25. These elements are connected together via a bus 23. The PMC section 12 includes a processor core 30, a first-level cache memory (L1 cache) 31, a second-level cache memory (L2 cache) 32, a DRAM 34, and a peripheral LSI 35. These elements are connected together via a bus 33. A machine side IO unit 16 is connected to the peripheral LSI 35 of the PMC section 12 via a field bus 17.
The servo motor control section 13 includes a servo control section processor 40 and a peripheral control LSI 45. These elements are connected together via a bus 43. The amplifier interface section 14 includes a peripheral control LSI 55. A motor control amplifier 18 is connected to the peripheral control LSI 55 of the amplifier interface section 14 via a serial servo bus 19. The numerical control section 11, the PMC section 12, the servo motor control section 13, and the amplifier interface section 14 are connected together via an internal bus 15.
The processor core 20 of the numerical control section 11, which is a main processor for the numerical controller 10 as a whole, reads calculation results from the PMC section 12 and the servo motor control section 13 via the internal bus 15 at each interruption that occurs at a given period. The processor core 20 executes a calculation based on the calculation results and writes a new calculation result to the PMC section 12 and the servo motor control section 13 also via the internal bus 15.
A controller such as a numerical controller that controls a machine tool needs to process a large-sized sequential program with a high priority at a given period within a predetermined time in order to control the position and speed of a servo motor in real time. The processing time for the sequential program significantly affects the performance of the numerical controller. An increased number of steps in the sequential program resulting from additional functions of the numerical controller tend to also increase the processing time. The extended processing time for the sequential program puts pressure on the processing time for other processes. Furthermore, given that the sequential program fails to complete processing within the predetermined time, the numerical controller does not function properly as a system that controls the machine tool.
The problem with the processing time for the sequential program has been solved exclusively by using techniques for increasing the speed of processors (operating frequency, pipeline, cache memory, branch history, and the like). In particular, an increased operating frequency of processors and an increased capacity of cache memories have made a significant contribution.
However, in recent years, the operating frequency of processors has leveled off due to the problem of an increase in power consumption and in the amount of heat generation. Thus, multi-core processors have prevailed in which a plurality of power-saving cores with a low operating frequency is mounted. Also for numerical controllers, a configuration using multi-core processors has been proposed as disclosed in Japanese Patent Application Laid-Open No. 2014-35564.
The multi-core processor is expected to improve performance by allowing the cores to execute threaded programs in parallel. On the other hand, in executing a sequential program, for which the use of threads is difficult, the multi-core processor poses the problem of increased cache misses as described below.
Many multi-core processors are configured such that the second- and subsequent-level cache memories are shared by the plurality of cores. In a multi-core processor with such a configuration, when, while a first core is executing the sequential program, a second core sharing the cache memories executes another program, the program rewrites the shared cache memories. Thus, compared to a single-core processor with the same capacity of cache memories, the multi-core processor is likely to cause cache misses in executing the sequential program.
If a cache miss occurs, the processor reads data needed to execute processing from a memory in which the sequential program is stored, and stores new data in the cache memories as needed. This needs much processing time compared to a case where the first core can utilize the cache memories.
Moreover, when a large-sized sequential process that exceeds the capacity of a first-level instruction cache memory is executed, the program fails to be entirely stored into the instruction cache memory. Thus, even while the sequential program is in execution, the instruction cache memory is rewritten, and a wait time for memory read extends the processing time for the program.
As a method for reducing the above-described cache misses, a prefetch function for the instruction cache memory is known which allows consecutive memory blocks to be prefetched into the instruction cache memory. Prefetching improves a cache hit rate but has difficulty in eliminating cache misses. For example, dynamic conditional branching may lead to a cache miss resulting from a failure in speculative prefetching. Furthermore, a memory read speed is low compared to the operating frequency of the processor, and thus, prefetching may fail to be performed in time, resulting in memory read wait.